XR16V554D

2.25V to 3.6V Quad UART with 16-Byte FIFO

Description

The XR16V5541 (V554) is a quad Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates of up to 4 Mbps at 3.3 V. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. An internal loopback capability allows onboard diagnostics. The V554 is available in a 48-pin QFN, 64-pin LQFP, 68-pin PLCC and 80-pin LQFP packages. The 64-pin and 80-pin packages only offer the 16 mode interface, but the 48- and 68-pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16V554IV (64-pin) offers three state interrupt output while the XR16V554DIV provides continuous interrupt output. The XR16V554 is compatible with the industry standard ST16C554.

NOTE: 1Covered by U.S. Patent #5,649,122

For UART technical support or to obtain an IBIS model for this product, please email Exar's UART Technical Support group.

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Features

  • Pin-to-pin compatible with ST16C454, ST16C554, TI’s TL16C554A and Philips' SC16C554B
  • Intel or Motorola Data Bus Interface select
  • Four independent UART channels
  • Register Set Compatible to 16C550
  • Data rates of up to 4 Mbps at 3.3 V and 3.125 Mbps at 2.5 V
  • 16 byte Transmit FIFO
  • 16 byte Receive FIFO with error tags
  • 4 Selectable RX FIFO Trigger Levels
  • Full modem interface
  • 2.25V to 3.6V supply operation
  • Crystal oscillator or external clock input
  • Pb-Free, RoHS Compliant Versions Offered

Application

  • Portable Appliances
  • Telecommunication Network Routers
  • Ethernet Network Routers
  • Cellular Data Devices
  • Factory Automation and Process Controls

Design Tools

Simulation Models
Package Type Vcc Temp Mode Version File
LQFP 3.3V Industrial Intel 1
LQFP 2.5V Industrial Intel 1
Evaluation Hardware and Software
Operating System Driver Version Release Date File
Linux 2.6.13 1.0.0 December 2009
Linux 2.6.18 1.0.0 December 2009
Windows XP & 2000 1.3.0.0 December 2009

Packaging

Pkg Code Details Quantities Dimensions PDF
LQFP64
  • JEDEC Reference: MO-026
  • MSL Pb-Free: L3 @ 260ºC
  • MSL SnPb Eutectic: n/a
  • ThetaJA: 50.0ºC/W
  • Bulk Pack Style: Tray
  • Quantity per Bulk Pack: 160
  • Quantity per Reel: 1000
  • Quantity per Tube: n/a
  • Quantity per Tray: 160
  • Reel Size (Dia. x Width x Pitch): 330 x 24 x 16
  • Tape & Reel Unit Orientation: Quadrant 2
  • Dimensions: mm
  • Length: 10.00
  • Width: 10.00
  • Thickness: 1.60
  • Lead Pitch: 0.50

Parts & Purchasing

Part Number Pkg Code RoHS Min Temp Max Temp Status Buy Now Order Samples
XR16V554DIV LQFP64 -40 85 OBS
XR16V554DIV-F LQFP64 -40 85 Active
XR16V554DIVTR-F LQFP64 -40 85 Active
Show obsolete parts
Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.

Quality Documents

Part NumberREACH
XR16V554DIVTR-FDownload
XR16V554DIV-FDownload
Additional Quality Documentation may be available, please contact customersupport@exar.com.
Distribution Date Description File
01/04/2017 Qualification of alternate assembly subcon, ANST. PCN 16-0623-01 ANST-1033.pdf
12/05/2013 Addition of an alternate qualified assembly site, ASE Chung-Li (Taiwan) for assembly using copper or gold wire bonding. Material change and alternate assembly site. PCN_13-0521-02-1033.pdf

Frequently Asked Questions

The best way to determine this is to go to exar.com and type the part into the search function. At or near the top of the results you should see something that looks like
 
 

In this example, we looked for XRA1201. When you hover over it, it will turn grey and you can click anywhere in the grey box. This brings you to the product page. For example:

 
 

Click on Parts & Purchasing, highlighted in yellow above. The screen changes to:

 

Notice the status column and the “Show obsolete parts” link:

 

A legend tells you the definition of the different statuses. Click on the “Show obsolete parts” link to see EOL or OBS part numbers along with the Active part numbers:

 
 

Another method to find out if a part is OBS or EOL is to click on SUPPORT:

 

And then Product Change Notifications

 
 

Type the part into the search, and click on one of the part numbers from the drop down menu. Then you can look for the Product Discontinuation Notice, which generally is at the top of the list, for example:

 
 

If you see this, it tells you that this particular orderable part has been discontinued and when the last order date is, or was. If you click on the file, then you can view the notice we sent about this if you purchased the part in the recent past. It may also advise of a replacement part. When an orderable part first becomes discontinued, Product Discontinuation Notices are sent are sent to those who have purchased the parts in the recent past, if purchased directly, with a dated opportunity to place a last order.

Yes, you can daisy-chain it like that, but only up to 2 times (3 UARTs total in the daisy-chain). The UARTs should be as close as possible.
It depends on the baud rate. For example, for a start bit, 8 data bits, no stop bit and 1 stop bit, the maximum baud rate deviation is 4.76%. For more information, see https://www.exar.com/appnote/dan108.pdf
For external clock frequencies above 24MHz at the XTAL1 input, a 2K pull-up may be necessary to improve the rise times if there are data transmission errors.
They crystal oscillator circuitry is recommended for fundamental frequency crystals only. The maximum frequency for crystals with fundamental frequencies is typically 24MHz. Above that frequency, crystals operate at higher harmonics, which will not work with the recommended crystal oscillator circuitry.
No. It is only required for transmitting and receiving data.
LSR bit-6 is a superset of LSR bit-5. The transmitter consists of a TX FIFO (or THR only when FIFOs are not enabled) and a Transmit Shift Register (TSR). When LSR bit-5 is set, it indicates that the TX FIFO (or THR) is empty, however there may be data in the TSR. When LSR bit-6 is set, it indicates that the transmitter (TX FIFO + TSR) is completely empty.
Yes, if you are using a UART with a fractional baud rate generator. This provides a divisor feature with a granularity of 1/16, allowing for any baud rate to be generated by any clock frequency, standard or non-standard. Click on the parametric search button of the product family page and find the Fractional Baud Rate Generator column which tells which products have this feature.
The UART will wake-up from sleep mode by any of the following conditions on any channel:
 
-Sleep mode is disabled
-Interrupt is generated
-Data is written into THR
-There is activity on the RX input pin
-There is activity on the modem input pins
 
If the sleep mode is still enabled and all wake-up conditions have been cleared, it will return to the sleep mode.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 
You can tell by reading LSR bit-5 or bit-6. If they are '0', then the transmit interrupt was generated by the trigger level. If they are '1', then the transmit interrupt was generated by the TX FIFO becoming empty. For enhanced UARTs, you can just read the FIFO level counters.
An RX Data Ready interrupt is generated when the number of bytes in the RX FIFO has reached the RX trigger level. An RX Data Timeout interrupt is generated when the RX input has been idle for 4 character + 12 bits time.
For some UARTs, the RX Data Timeout interrupt has a higher priority and in others, the RX Data Ready interrupt has a higher priority. See the interrupt priority section of the datasheet.
The UART requires a clock and a valid baud rate in order to transmit and receive data. Check that there is a clock signal on the XTAL1 input pin. Also, valid divisors need to be written into the DLL and DLM registers. Most UARTs have random (invalid) values upon power-up.
For most UARTs, the interrupt is generated when the data is ready to be read from the RX FIFO. The are some UARTs that generate the interrupt when the character with the error is received. There are some UARTs that have a register bit to select whether the LSR interrupt is generated immediately or delayed until it is ready to be read.
For any UART that has the wake-up indicator interrupt, an interrupt will be generated when the UART wakes up even if no other interrupts are enabled.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 
No, Auto RTS and Auto CTS are independent. Auto RTS is toggled by the UART receiver. Auto CTS is monitored by the UART Transmitter.
The UART will enter the sleep mode if the following conditions have been satisfied for all channels:
 
-Sleep Mode is enabled
-No interrupts are pending
-TX and RX FIFOs are empty
-RX input pin is idling HIGH (LOW in IR mode)
-Valid values in DLL and DLM registers
-Modem input pins are idle (MSR bits 3-0=0x0)
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode
There will be no activity on the XTAL2 output.
 
See AN204, UART Sleep Mode for more information on UART Sleep Mode 
No, Auto RTS and Auto CTS will work normally without the interrupts enabled.
Auto RS485 Half-Duplex Control feature overrides the Auto RTS flow control feature if both features use the RTS# output pin. Both features can only be used simultaneously if the Auto RS485 control output is not the RTS# output. For some UARTs, the Auto RS485 control output is not the RTS# output.
No, software flow control characters are not loaded into the RX FIFO.
Since 2-character software flow control requires that 2 consecutive flow control characters match before data transmission is stopped or resumes, there is less of a chance that data transmission is stopped because one data byte matched a control character.
The polarity of the RS485 control output varies from one UART to another. For some UARTs, an inverter may be required. Some of the newer UARTs have register bits that can change that polarity of the RS485 control output.
It is recommended that the FIFO counters at the Scratchpad Register location be used. When transmitting or receiving data, writing to the LCR register could result in transmit and/or receive data errors.
Due to the dynamic nature of the FIFO counters, it is recommended that the FIFO counter registers be read until consecutive reads return the same value.
In the normal mode, the TX interrupt is generated when the TX FIFO is empty, and there may still be data in the Transmit Shift Register. In the RS485 mode, the TX interrupt is generated when the TX FIFO and the TSR register are both empty.
All of the UARTs that have the IR mode supports up to 115.2Kbps as specified in IrDA 1.0. The newer I2C/SPI UARTs can support up to 1.152Mbps as specified in IrDA 1.1.
Most UARTs use RTS#, however the XR16C850 and XR16C864 use the OP1# output as the Auto RS485 control output. In addition to using the RTS# output as the Auto RS485 control output, the XR16L784, XR16L788 and XR16V798 can use the DTR# output as the Auto RS485 control output.

Yes. Note: some devices do have powersave mode. If UART goes into powersave mode, then the registers are not accessible.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

 

  • Check whether the register set can be accessed.
  • Check whether the crystal is oscillating fully.
  • Check whether the data can be transmitted in internal loopback mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Please check that all the following conditions are satisfied first.

 

  • no interrupts pending (ISR bit-0 = 1)
  • modem inputs are not toggling (MSR bits 0-3 = 0)
  • RX input pin is idling HIGH • divisor (the value in DLL register) is non-zero
  • TX and RX FIFOs are empty

 

Be sure sleep mode bit has been set to 1. If there are multiple UART channels, the sleep conditions must be true for all channels.

 

See more on Sleep Mode in AN204 UART Sleep Mode.

Read LSR register to check whether the UART receives the data or not.

 

  • If LSR value is 0x60, it means that either UART receiver FIFO doesn’t receive the data or the data in receiver FIFO has been read out before the read of LSR.
  • If LSR value is 0x00, it means data is still in the THR (clock doesn’t oscillate to transmit data).
  • If LSR value is 0xFF, it means either UART is in powersave mode or UART is powered off. For those devices with powersave mode, be sure that UARTS are not in powersave mode.

 

 

See more on Sleep Mode in AN204 UART Sleep Mode.

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