XR81111

Universal Clock - High Frequency LVPECL Clock Synthesizer
Data Sheets OBS (Obsolete)

Overview

Outputs (#) 1
Output Type LVCMOS/ LVDS/ LVPECL
Output Frequency (MHz) 10-1500
Inputs (#) 1
Input Type Crystal, LVCMOS
Input Frequency (MHz) 10-60
Sup V 2.5/3.3
IDD (mA) 88
Typ Jitter 0.6 ps (12K-20M)
Operating Temp Range (°C) -40°C to +85°C
Package QFN10
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The XR81111 is a family of Universal Clock synthesizer devices in a 5mm x 7mm QFN-10 package. The devices generate ANY frequency in the range of 10 MHz to 1.5GHz by utilizing a highly flexible delta sigma modulator and a wide ranging VCO. The high clock frequency LVCMOS/LVDS/LVPECL outputs have very low phase noise jitter of sub 0.6ps, while consuming extremely low power. These devices can be used with standard crystals or external system clock and can be configured to select from four different frequency multiplier settings to support a wide variety of applications. This family of products have an extremely low power PLL block with core power consumption less than 40% of the equivalent devices from competition.

The block diagram shows a typical synthesizer configuration with any standard crystal oscillating in fundamental mode. Internal load capacitors are optionally available to eliminate external crystal loads. A system clock can also be used to overdrive the oscillator for a synchronous timing system. The differential LVDS/LVPECL and single ended CMOS outputs have industry standard interface loading configuration.

The typical phase noise plot shows the jitter integrated over the 12KHz to 20MHz range that is widely used in WAN systems. Most LAN applications however use the integration range of 1.875MHz to 20MHz.These clock devices show a very good high frequency noise floor below - 150dB.

  • Footprint compatible with 5mm x 7mm differential oscillators
  • One differential LVDS/LVPECL output pair
  • Single ended LVCMOS output
  • Crystal oscillator interface which can also be overdriven using a single-ended reference clock
  • Output frequency range: 10MHz -1.5GHz
  • Crystal/input frequency range: 10MHz - 60MHz, parallel resonant crystal
  • VCO range: 2GHz - 3GHz
  • RMS phase jitter 12kHz - 20MHz: <0.60ps (typical)
  • Full 3.3V or 2.5V operating supply
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) QFN-10 package
Configure & Sample: Universal Clocks

  • 10GE, GE LAN/WAN
  • 2.5G/10G SONET/SDH/OTN
  • xDSL, PCIe
  • Low-jitter Clock Generation
  • Synchronized clock systems

Documentation & Design Tools

Type Title Version Date File Size
Data Sheets XR81111 Universal Clock - High Frequency LVPECL Clock Synthesizer 1B April 2014 234 KB
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Parts & Purchasing

Part Number Pkg Code Min Temp Max Temp Status Suggested Replacement PDN
XR81111-CA04-F QFN10 -40 85 OBS
XR81111-CA04TR-F QFN10 -40 85 OBS
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Part Status Legend
Active - the part is released for sale, standard product.
EOL (End of Life) - the part is no longer being manufactured, there may or may not be inventory still in stock.
CF (Contact Factory) - the part is still active but customers should check with the factory for availability. Longer lead-times may apply.
PRE (Pre-introduction) - the part has not been introduced or the part number is an early version available for sample only.
OBS (Obsolete) - the part is no longer being manufactured and may not be ordered.
NRND (Not Recommended for New Designs) - the part is not recommended for new designs.

Packaging

Pkg Code Details Quantities Dimensions PDF
QFN10
  • JEDEC Reference:
  • MSL Pb-Free: L2 @ 260ºC
  • MSL SnPb Eutectic:
  • ThetaJA: 39.2ºC/W
  • Bulk Pack Style: Tray
  • Quantity per Bulk Pack: 490
  • Quantity per Reel: 3000
  • Quantity per Tube: n/a
  • Quantity per Tray: 490
  • Reel Size (Dia. x Width x Pitch): 330 x 16 x 12
  • Tape & Reel Unit Orientation: Quadrant 1
  • Dimensions: mm
  • Length: 7.0
  • Width: 5.0
  • Thickness: 1.0
  • Lead Pitch: 1.0 and 2.54

Notifications

Distribution Date Description File
07/11/2017 Product Discontinuation Notification
12/22/2016 Change in Package 10L QFN lead dimensions, lead position from edge and delete L/F paddle.